The invention relates generally to methods of fabricating silicon carbide based metal oxide field effect transistors (MOSFETs) and in particular to self-aligned methods of fabricating silicon carbide based MOSFETs.
Silicon carbide (SiC) is an attractive alternative to silicon (Si) for high voltage, high power applications due to the inherent material properties of SiC. For example, SiC exhibits a wide band gap and a high thermal conductivity that facilitates elevated temperature operation.
For certain devices such as, SiC vertical metal oxide field effect transistors (MOSFET), close packing of adjacent cells is desirable, to enhance on-resistance and switching performance. To increase cell packing density, the spacing between the gate and source contacts must be reduced. However, a reduction in the gate to source contact spacing typically reduces the manufacturable yield of SiC MOSFETs.
Therefore, it is desirable to provide a method that addresses these issues related to the spacing between gate and source contacts in vertical SiC MOSFETs. It is also desirable to increase the manufacturable yield of closely packed vertical MOSFET devices. Accordingly, a technique is needed to address one or more of the foregoing problems in the fabrication of SiC MOSFET devices.